Oscillating signals are used in many electronic systems, for many different purposes. For example, an oscillating signal may be used as a clock signal in an electronic system for timing actions of the system correctly (e.g., to synchronize operations of the system). Oscillating signals may be used for other purposes also. In digital circuits, an oscillating clock signal transitions between a high level and a low level and at least some of the transitions occur at regular intervals to provide a regular clock signal. The oscillating signal has a duty cycle which is given by the proportion of time for which the signal has a high value. For example, a clock signal has a duty cycle of 50% when for half of the clock period the clock signal has a high value and for the other half of the clock period the clock signal has a low value. If a clock signal has a duty cycle of more than 50% then the clock signal is high for more than half of the clock period, and the clock signal is low for less than half of the clock period. In contrast, if a clock signal has a duty cycle of less than 50% then the clock signal is high for less than half of the clock period, and the clock signal is low for more than half of the clock period.
It is often desirable to have a clock signal which has a duty cycle of 50%. With a duty cycle of 50%, each transition on the clock signal occurs at a regular time interval following the previous transition. This allows a circuit which is driven by the clock signal to use both the rising and falling edges of the clock signal to trigger synchronous circuits to achieve a faster operating speed.
A local oscillator may generate an oscillating signal for use in an electronic system. For a number of reasons, the signal generated by the local oscillator may not have a duty cycle of 50%. For example, mismatches in components of the local oscillator may result in the duty cycle of the oscillating signal being different from 50%. Therefore, a duty cycle correction circuit may be used to adjust the duty cycle of the signal generated by the local oscillator before the oscillating signal is used in the rest of the electronic system.
The circuit 100 shown in FIG. 1 acts as a buffer to provide a rail-to-rail Local Oscillator (LO) signal, e.g., to mixers. Generally, LO circuitry can be far away from the mixers on a chip, which can cause attenuation in the LO signal provided to the mixers. The circuit 100 also provides some inherent duty cycle correction, as described below. The circuit 100 comprises an input line 102 for receiving an input signal from a local oscillator (LO-IN) and an output line 104 for outputting an adjusted signal (LO-OUT). The output signal has the same frequency as the input signal, but the duty cycle of the output signal may be adjusted relative to the input signal. The circuit 100 also comprises an AC coupling capacitor 106, a first inverter 108, a second inverter 110, and a resistor 112. The input line 102 is coupled to an input of the AC coupling capacitor 106. An output of the AC coupling capacitor 106 is coupled to a data input of the first inverter 108. An output of the first inverter 108 is coupled to a data input of the second inverter 110. An output of the second inverter 110 is coupled to the output line 104. The output of the first inverter 108 is coupled to the data input of the first inverter 108 via the resistor 112. The first and second inverters 108 and 110 are connected to a supply voltage and to a ground voltage. The ground voltage is also coupled to the output line 104 via a coupling capacitor as shown in FIG. 1.
In operation an input signal is received from the local oscillator on the input line 102 and passed to the AC coupling capacitor 106. The AC coupling capacitor 106 allows the AC components of the input signal to pass through to the rest of the circuit 100, but the DC components of the input signal are blocked. In this way the DC bias of the input signal is isolated from the rest of the circuit 100. The input signal then passes from the AC coupling capacitor 106 to the data input of the first inverter 108. The output of the first inverter 108 is the inverse of the data input to the first inverter 108. Therefore, when the value of the input signal at the data input of the first inverter 108 is high, then the value of the output of the first inverter 108 is low. Likewise, when the value of the input signal at the data input of the first inverter 108 is low, then the value of the output of the first inverter 108 is high. The output of the first inverter 108 is fed back to the input of the first inverter 108 via the resistor 112. The result of this resistor feedback is explained in more detail below with reference to FIGS. 3a and 3b. The signal passes from the first inverter 108 to the second inverter 110, where the signal is inverted once again and passed to the output line 104. Therefore, the output signal on the output line 104 has the same frequency as the input signal on the input line 102 and has the same polarity (i.e., there is an even number of inverters—in this case two).
FIG. 2 shows a circuit diagram of a CMOS inverter 200 which may be used for the inverters 108 and 110 in the circuit 100. It would be apparent to a person skilled in the art that the first and second inverters 108 and 110 could be implemented as any other suitable type of inverter instead of as a CMOS inverter. The CMOS inverter 200 includes a supply line 202 connected to a supply voltage, a ground line 204 connected to a ground voltage, a data input line 206 for receiving an input signal, an output line 208 for outputting an output signal, a PMOS transistor 210, and an NMOS transistor 212. The input signal is received on data input line 206 and passed to the gate of the PMOS transistor 210 and is also passed to the gate of the NMOS transistor 212. The drains of both the PMOS transistor 210 and the NMOS transistor 212 are connected to the output line 208. The supply line 202 supplies a positive voltage (Vdd) to the source terminal of the PMOS transistor 210. The ground line 204 supplies a ground voltage (Gnd) to the source terminal of the NMOS transistor 212. When the input signal is high, current flows through the NMOS transistor 212 but not through the PMOS transistor 210, such that the output signal on output line 208 is brought to a low value. When the input signal is low, current flows through the PMOS transistor 210 but not through the NMOS transistor 212, such that the output signal on output line 208 is brought to a high value.
The circuit 100 provides some duty cycle correction of the input signal as described with reference to FIGS. 3a and 3b. FIGS. 3a and 3b show the value (i.e., the voltage level) of the signal as a function of time. The supply voltage VDD is shown at a high level and the ground voltage GND is shown at a low level. The supply voltage (VDD) and ground voltage (GND) are supplied to the inverters 108 and 110. The line 302 shows the value of the input signal arriving on input line 102 prior to reaching the AC coupling capacitor 106. The line 304 shows the value of the input signal once it has passed through the AC coupling capacitor 106. As described above, the AC coupling capacitor isolates the DC bias of the input signal from the rest of the circuit 100, and this is why the DC value of the input signal can change after the AC coupling capacitor 106, but the AC components of the input signal do not significantly change due to the AC coupling capacitor 106. The line 306 shows the switching point of the second inverter 110. The switching point is the voltage level at which the second inverter 110 has a transition between recognizing the input signal as having a high value and recognizing the input signal as having a low value. It can be appreciated from FIGS. 3a and 3b that the switching point of the second inverter 110 is chosen as half of the supply voltage, VDD. The line 308 shows the switching point of the first inverter 108 (i.e., the DC voltages at the input and output of the first inverter 108) due to the resistive feedback through the resistor 112. For simplification, the graphs shown in FIGS. 3a and 3b have assumed zero attenuation of the input signal (e.g., zero input capacitance) through the AC coupling capacitor 106.
FIG. 3a shows an imperfect input signal (as line 302) received at the signal chain shown in FIG. 1 from a local oscillator. The input signal is imperfect in the sense that the duty cycle of the input signal is less than 50%. This can be seen in FIG. 3a in that t1H (the duration for which the input signal 302 is at logic High) is less than t1L (the duration for which the input signal 302 is at logic Low). The DC operating point after the AC coupling capacitor 106 (as shown by line 308) is set by the resistive feedback through the resistor 112 and the AC coupling capacitor 106. Since t1H is lower than t1L, the on-time for the PMOS transistor 210 of the first inverter 108 is longer than the on-time of the NMOS transistor 212. Therefore, the output of the first inverter 108 has a high value for a longer duration than it has a low value. Due to the feedback through the resistor 112, this shifts the whole waveform of the input signal at the input of the first inverter 108, shown by line 304, up (relative to line 302), as shown in FIG. 3a. In other words, the DC operating point or switching point of the input signal at the first inverter 108 is increased (as shown by line 308). Meanwhile, the switching point of the second inverter 110 does not change as shown with line 306. It can be seen from FIG. 3a that the output signal has a high value for a time period t2H and the output signal has a low value for a time period t2L. It can also be seen that in the situation shown in FIG. 3a the duty cycle of the output signal is higher than the duty cycle of the input signal. In other words, when the duty cycle of the input signal is less than 50%, the duty cycle of the output signal is greater than the duty cycle of the input signal, i.e.
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FIG. 3b shows an imperfect input signal (as line 302) received at the signal chain shown in FIG. 1 from the local oscillator. The input signal is imperfect in the sense that the duty cycle of the input signal is more than 50%. This can be seen in FIG. 3b in that t1H (the duration for which the input signal 302 is at logic High) is more than t1L (the duration for which the input signal 302 is at logic Low). The DC operating point after the AC coupling capacitor 106 (as shown by line 308) is set by the resistive feedback through the resistor 112 and the AC coupling capacitor 106. Since t1H is greater than t1L, the on-time for the PMOS transistor 210 of the first inverter 108 is shorter than the on-time of the NMOS transistor 212. Therefore, the output of the first inverter 108 has a high value for a shorter duration than it has a low value. Due to the feedback through the resistor 112, this shifts the whole waveform of the input signal at the input of the first inverter 108, shown by line 304, down (relative to line 302), as shown in FIG. 3b. In other words, the DC operating point or switching point of the input signal at the first inverter 108 is decreased (as shown by line 308). Meanwhile, the switching point of the second inverter 110 does not change as shown with line 306. It can be seen from FIG. 3b that the output signal has a high value for a time period t2H and the output signal has a low value for a time period t2L. It can also be seen that in the situation shown in FIG. 3b the duty cycle of the output signal is lower than the duty cycle of the input signal. In other words, when the duty cycle of the input signal is more than 50%, the duty cycle of the output signal is less than the duty cycle of the input signal,
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It can therefore be seen that the circuit 100 has some inherent duty cycle correction due to the AC coupling capacitor 106 and the duty cycle dependent DC operating voltage at the input of the first inverter 108 (provided by the resistor feedback). However, the inherent correction of circuit 100 is not always sufficient to correct the whole duty cycle mismatch. This can be seen in FIGS. 3a and 3b in that although the duty cycle has improved (relative to the input signal), the duty cycle of the output signal is still not equal to 50% in the examples shown in FIGS. 3a and 3b. Furthermore, the circuit 100 is inflexible in the sense that it only adjusts the duty cycle of the input signal towards 50%. Therefore if a duty cycle other than 50% is desired for the input signal then the circuit 100 may not be suitable for adjusting the duty cycle of the input signal to the desired duty cycle.